In the configuration of conventional computer systems, a plurality of LSIs and so on are mounted on a mother board. In many cases, it becomes necessary to reset these LSIs simultaneously or conduct some setting on these LSIs simultaneously. In such computer systems, therefore, respective LSIs are connected to a system synchronizing signal supply unit, which supplies a system synchronizing signal, in parallel by signal wires. By utilizing the system synchronizing signal transmitted via the signal wires, respective LSIs ensure the synchronization of operation timing.
The distance between the system synchronizing signal supply unit and each LSI differs depending upon the position where the LSI is disposed. If these LSIs are connected simply, therefore, the system synchronizing signal is delayed by the signal wire. As a result, there occurs discrepancy in operation timing.
In order to prevent the transmission delay of the synchronizing signal caused by the disposition position of such LSIs, therefore, line lengths of respective signal wires are adjusted in the prior art so that line lengths of signal wires as far as respective LSIs may become equal.
If the line lengths of signal wires are adjusted as in the prior art, however, the line length of the signal wire as far as each LSI must be made equal to the longest line length. This results in a problem of an increased amount of signal wire and complicated disposition of signal wires.
Especially, if the system scale becomes large and the synchronization of operation timing of devices disposed so as to extend over a plurality of casings must be maintained, then the line length becomes very long and such a situation cannot be coped with mere line length adjustment.
In the case where a plurality of devices (such s LSIs) operate at the same operation timing, therefore, how to ensure the synchronization of such operation timing becomes an extremely important problem.